The present invention relates generally to semiconductor device structures, and more particularly to forming capacitors in an integrated circuit.
Capacitors are critical components in an integrated circuit (IC), de-coupling power supply lines or forming series inductance-capacitor circuit for noise immunization and high speed radio frequency (RF) applications. For example, in an IC having analog circuits, capacitors are often placed near the analog circuits to de-coupling or stabilizing a power supply to the analog circuits.
A semiconductor capacitor is typically constructed with an insulator or dielectric material sandwiched between two parallel conductive plates. When a voltage difference is applied across the plates, a certain electrical charge is stored in the insulator. The amount of electrical charge stored in the insulator is defined by the capacitance of the capacitor. Both polysilicon and metal are used to form the conductive plates. However, metal-oxide-metal (MOM) capacitors have seen their increased popularity because of their minimal capacitive loss to the substrate and compatibility with logic processes.
Conventional MOM capacitors are constructed in such structures as a vertical stack, U-shape plates or horizontal stacks. The vertical stack structure is a bottom conductive plate first covered by a thin dielectric layer, then covered by a top conductive plate on top of the dielectric layer. A capacitor is formed by the vertically stacked conductor/dielectric/conductor. This kind of vertical stack structure may occupy large areas. Forming such capacitor and making connection thereto may require at least two to four layers of material depositions as well as additional two to three masking steps. The U-shape plate structure employs damascene like processes that include oxide deposition, U-shape opening, bottom plate deposition, thin dielectric deposition, top plate deposition, U-shape fill and chemical-mechanical-planarization (CMP) or etch back process steps. Both the vertical stack and U-shape plate structures require complex additional process steps and additional cost on lithograph, etching and deposition.
The horizontal stack is the most simple and lowest costly (no additional process steps or complexity) structure among the three conventional structures for forming a semiconductor capacitor. The horizontal stack structure employs coupling capacitances between sidewalls of two adjacent metal lines. The most popular layout style is to place multiple cathode and anode metal lines of a capacitor alternatively next to each other in a cross-finger style. Between these metal lines is an inter-metal-dielectric (IMD) material serving as capacitor's insulator. A major drawback of the horizontal stack structure is its low unit length capacitance due to limited height and large space of the metal lines. However, as process technologies shrink down to 100 nm generation and beyond, both metal line width and space become small enough to allow the horizontal stack structure to be competitive area wise as well, when the cross-finger layout style is employed.
FIG. 1 is a cross-sectional view of an improved conventional horizontal stack capacitor structure 100 which employs not only the sidewalls of two metal lines 115 and 125, but also the sidewalls of two via lines 110 and 120 as capacitor conductors. The capacitor structure 100 is formed on a dielectric layer 150. The via lines 110 and 120 are formed in an inter-layer dielectric (ILD) 130. The metal lines 115 and 125 are formed in an inter-metal dielectric (IMD) 140. Both the ILD and IMD serves as insulators for the capacitor structure 100, therefore, its capacitor area becomes larger. However, a design rule may require that the metal lines 115 and 125 to overlay the via lines 110 and 120, respectively, and at the same time, the metal lines 115 and 125 have to maintain a minimum spacing D. As a result, the insulator of the capacitor structure 100 may not be very thin to achieve a large unit length capacitance value.
As such, what is desired is a simple, reliable and low cost semiconductor capacitor with high capacitance per unit area for advanced process technologies.